/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_DMAC_HW_H
#define RK_DMAC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the DMAC.
 */
#define RK_DMAC_DSR_OFFSET       0x0000U /* DMA Manager Status Register */
#define RK_DMAC_DPC_OFFSET       0x0004U /* DMA Program Counter Register */
#define RK_DMAC_INTEN_OFFSET     0x0020U /* Interrupt Enable Register */
#define RK_DMAC_EVENT_RIS_OFFSET 0x0024U /* Event-Interrupt Raw Status Register */
#define RK_DMAC_INTMIS_OFFSET    0x0028U /* Interrupt Status Register */
#define RK_DMAC_INTCLR_OFFSET    0x002CU /* Interrupt Clear Register */
#define RK_DMAC_FSRD_OFFSET      0x0030U /* Fault Status DMA Manager Register */
#define RK_DMAC_FSRC_OFFSET      0x0034U /* Fault Status DMA Channel Register */
#define RK_DMAC_FTRD_OFFSET      0x0038U /* Fault Type DMA Manager Register */

#define RK_DMAC_FTR_OFFSET(x)    (0x0040U + 0x04 * (x)) /* Channel x Fault Type Register */
#define RK_DMAC_CSR_OFFSET(x)    (0x0100U + 0x08 * (x)) /* Channel x Status Register */
#define RK_DMAC_CPC_OFFSET(x)    (0x0104U + 0x08 * (x)) /* Channel x Program Counter Register */
#define RK_DMAC_SAR_OFFSET(x)    (0x0400U + 0x20 * (x)) /* Channel x Source Address Register */
#define RK_DMAC_DAR_OFFSET(x)    (0x0404U + 0x20 * (x)) /* Channel x Destination Address Register */
#define RK_DMAC_CCR_OFFSET(x)    (0x0408U + 0x20 * (x)) /* Channel x Channel Control Register */
#define RK_DMAC_LC0_OFFSET(x)    (0x040CU + 0x20 * (x)) /* Channel x Loop Counter 0 Register */
#define RK_DMAC_LC1_OFFSET(x)    (0x0410U + 0x20 * (x)) /* Channel x Loop Counter 1 Register */

#define RK_DMAC_DBGSTATUS_OFFSET 0x0D00U /* Debug Status Register */
#define RK_DMAC_DBGCMD_OFFSET    0x0D04U /* Debug Command Register */
#define RK_DMAC_DBGINST0_OFFSET  0x0D08U /* Debug Instruction-0 Register */
#define RK_DMAC_DBGINST1_OFFSET  0x0D0CU /* Debug Instruction-1 Register */
#define RK_DMAC_CR0_OFFSET       0x0E00U /* Configuration Register 0 */
#define RK_DMAC_CR1_OFFSET       0x0E04U /* Configuration Register 1 */
#define RK_DMAC_CR2_OFFSET       0x0E08U /* Configuration Register 2 */
#define RK_DMAC_CR3_OFFSET       0x0E0CU /* Configuration Register 3 */
#define RK_DMAC_CR4_OFFSET       0x0E10U /* Configuration Register 4 */
#define RK_DMAC_CRDn_OFFSET      0x0E14U /* Configuration Register */
#define RK_DMAC_WD_OFFSET        0x0E80U /* DMA Watchdog Register */

#ifdef __cplusplus
}
#endif

#endif /* RK_DMAC_HW_H */